Functional Descriptions; Master/Slave Mode - Samsung S5PC110 Manual

S5PC110_UM

2.4 FUNCTIONAL DESCRIPTIONS

IIS interface consists of register bank, FIFOs, shift registers, clock control, DMA finite state machine, and channel
control block as shown in
left/right channel data. Thus, FIFO access and data transfer are handled with left/right pair unit. Figure 2-1 shows
the functional block diagram of IIS interface.

2.4.1 MASTER/SLAVE MODE

Master/Slave mode shows direction of I2SLRCLK and I2SSCLK. If IIS bus interface transmits I2SLRCLK and
I2SSCLK to IIS codec, IIS bus is master mode. If IIS bus interface receives I2SLRCLK and I2SSCLK from IIS
codec, IIS bus is slave mode. To select master or slave mode, set MSS bit of IISMOD register.
TX/RX mode indicates the direction of data flow. If IIS bus interface transmits data to IIS codec, this indicates TX
mode. Conversely, IIS bus interface receives data from IIS codec, this indicates RX mode.
shows AUDIO BUS CLK. For more information, refer to 10.01.S5PC110_Low Power Audio Subystem.
Figure 2-2
XXTI or FOUT_EPLL
IISCDCLK0 PAD
(Clock from external
I2S master)
SCLK_AUDIO0
2-1. Note that each FIFO has 32-bit width and 64-depth structure, which contains
Figure
MUX
0
1
2
Figure 2-2 Clock Controller in Audio Sub-System
DIVIDER
(1~16)
I2S
DIVIDER
(1~16)
2 IIS MULTI AUDIO INTERFACE
BUSCLK
I2SCLK
2-3