Table of Contents
Advertisement
RESET
Voltage [V]
V
DD
The system reset operation depends on the interlocking work of the reset pin, LVD circuit and Internal
POR. The LVD circuit can be disabled and enabled in the stop mode by smart option. If 3FH.7 is '1', LVD
circuit is always enabled. In this case the system reset by LVD circuit occurs in stop mode. But, if 3FH.7 is
'0', the system reset by LVD circuit doesn't occur in stop mode. Refer to page 2-3 relating to the smart
option. The rising time of VDD must be less than 1ms. If not, IPOR can't detect power on reset.
8-6
Figure 8-5. Timing Diagram for Internal Power-On Reset Circuit
T
= 1ms
VDD
(V
Rising Time)
DD
V
IH
Reset Pulse Width
NOTE
Va
= 0.85 V
DD
V
= 0.4 V
IL
DD
Reset pulse
S3F80JB
V
DD
Time
Advertisement
Table of Contents
