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Exception Processing Overview
Instruction
BITREV
BYTEREV
FF1
STLDSR
2.5
Exception Processing Overview
Exception processing for ColdFire processors is streamlined for performance. The
ColdFire processors differ from the M68000 family in that they include:
• A simplified exception vector table
• Reduced relocation capabilities using the vector base register
• A single exception stack frame format
• Use of a single self-aligning system stack
All ColdFire processors use an instruction restart exception model, but certain
microarchitectures (V2 and V3) require more software support to recover from certain
access errors. See Section 2.7.1, "Access Error Exception" for details.
Exception processing includes all actions from the detection of the fault condition to the
initiation of fetch for the first handler instruction. Exception processing is comprised of
four major steps
First, the processor makes an internal copy of the SR and then enters supervisor mode by
asserting the S bit and disabling trace mode by negating the T bit. The occurrence of an
interrupt exception also forces the M bit to be cleared and the interrupt priority mask to be
set to the level of the current interrupt request.
Second, the processor determines the exception vector number. For all faults except
interrupts, the processor performs this calculation based on the exception type. For
interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to obtain the
vector number from the interrupt controller. The IACK cycle is mapped to a special
acknowledge address space with the interrupt level encoded in the address.
2-10
Table 2-4. ISA Revision A+ New Instructions
The contents of the destination data register are bit-reversed; that
is, new Dx[31] = old Dx[0], new Dx[30] = old Dx[1], ..., new Dx[0]
= old Dx[31].
The contents of the destination data register are byte-reversed;
that is, new Dx[31:24] = old Dx[7:0], ..., new Dx[7:0] = old
Dx[31:24].
The data register, Dx, is scanned, beginning from the
most-significant bit (Dx[31]) and ending with the least-significant
bit (Dx[0]), searching for the first set bit. The data register is then
loaded with the offset count from bit 31 where the first set bit
appears.
Pushes the contents of the Status Register onto the stack and
then reloads the Status Register with the immediate data value.
MCF5282 User's Manual
Description
MOTOROLA
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