Timer Status Register (Tsr) - Motorola MC68HC05T16 Technical Data Manual

When IEDG is set, a positive-going edge on the TCAP pin will trigger a transfer of the free-running
counter value to the input capture registers. When clear, a negative-going edge triggers the
transfer.
5.1.5

Timer Status Register (TSR)

Address
$11
The Timer Status register contains the status bits for the above four interrupt conditions - ICF,
5
OC0F, OC1F, TOF.
Accessing the timer status register satisfies the first condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
ICF - Input Capture Flag
1 (set)
0 (clear) –
This bit is set when the selected polarity of edge is detected by the input capture edge detector;
an input capture interrupt will be generated, if ICIE is set, ICF is cleared by reading the TSR and
then the Input Capture Low register ($13)
OC0F - Output Compare 0 Flag
1 (set)
0 (clear) –
OC0F will be set when its output compare 0 register contents match that of the free-running
counter; an output compare interrupt will be generated, if OC0IE is set. OC0F is cleared by
reading the TSR and then the Output Compare 0 Low register ($15).
OC1F - Output Compare 1 Flag
1 (set)
0 (clear) –
OC0F will be set when its output compare 1 register contents match that of the free-running
counter; an output compare interrupt will be generated, if OC1IE is set. OC1F is cleared by
reading the TSR and then the Output Compare 1 Low register ($17).
MOTOROLA
5-6
bit 7 bit 6 bit 5
ICF OC0F OC1F
– A valid input capture has occurred.
No input capture has occurred.
– A valid output compare has occurred on output compare 0 register.
No output compare has occurred on output compare 0 register.
– A valid output compare has occurred on output compare 1 register.
No output compare has occurred on output compare 1 register.
bit 4 bit 3 bit 2
TOF TCAPS
TIMERS
State
bit 1 bit 0
on reset
0000 u000
MC68HC05T16
TPG