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Processor Register Description
• Two 32-bit access control registers (ACR0, ACR1)
• Two 32-bit memory base address registers (RAMBAR, FLASHBAR)
31
The following paragraphs describe the supervisor programming model registers.
2.2.3.1
Status Register (SR)
The SR stores the processor status and includes the CCR, the interrupt priority mask, and
other control bits. In supervisor mode, software can access the entire SR. In user mode, only
the lower 8 bits are accessible (CCR). The control bits indicate the following states for the
processor: trace mode (T bit), supervisor or user mode (S bit), and master or interrupt state
(M bit). All defined bits in the SR have read/write access when in supervisor mode.
System Byte
15
14
13
12
T
0
S
M
Bits
15
14
13
2-6
15
Figure 2-5. Supervisor Programming Model
11
10
0
I
Figure 2-6. Status Register
Table 2-2. SR Field Descriptions
Name
T
Trace enable. When set, the processor performs a trace exception after
every instruction.
—
Reserved, should be cleared.
S
Supervisor/user state. Denotes whether the processor is in supervisor
mode (S = 1) or user mode (S = 0).
MCF5282 User's Manual
7
0
(CCR)
SR
OTHER_A7
VBR
CACR
ACR0
ACR1
FLASHBAR
RAMBAR
Condition Code Register (CCR)
8
7
6
5
0
0
0
Description
STATUS
SUPERVISOR A7
STACK POINTER
VECTOR BASE
REGISTER
CACHE
CONTROL
ACCESS
CONTROL
ACCESS
CONTROL
FLASH BASE
ADDRESS REGISTER
RAM BASE
ADDRESS REGISTER
4
3
2
1
X
N
Z
V
MOTOROLA
0
C
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