ST STM32F405 Reference Manual page 1097

RM0090
–
–
32.9 CAN registers
The peripheral registers have to be accessed by words (32 bits).
32.9.1 Register access protection
Erroneous access to certain configuration registers can cause the hardware to temporarily
disturb the whole CAN network. Therefore the CAN_BTR register can be modified by
software only while the CAN hardware is in initialization mode.
Although the transmission of incorrect data will not cause problems at the CAN network
level, it can severely disturb the application. A transmit mailbox can be only modified by
software while it is in empty state, refer to
The filter values can be modified either deactivating the associated filter banks or by setting
the FINIT bit. Moreover, the modification of the filter configuration (scale, mode and FIFO
assignment) in CAN_FMxR, CAN_FSxR and CAN_FFAR registers can only be done when
the filter initialization mode is set (FINIT=1) in the CAN_FMR register.
32.9.2 CAN control and status registers
Refer to
CAN master control register (CAN_MCR)
Address offset: 0x00
Reset value: 0x0001 0002
31 30 29
15 14 13
RESET
rs
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 DBF: Debug freeze
Bit 15 RESET: bxCAN software master reset
Bits 14:8 Reserved, must be kept at reset value.
Wakeup condition, SOF monitored on the CAN Rx signal.
Entry into Sleep mode.
Section 1.1 for a list of abbreviations used in register descriptions.
28 27 26 25
12 11 10 9
Reserved
0: CAN working during debug
1: CAN reception/transmission frozen during debug. Reception FIFOs can still be
accessed/controlled normally.
0: Normal operation.
1: Force a master reset of the bxCAN -> Sleep mode activated after reset (FMP bits and
CAN_MCR register are initialized to the reset values). This bit is automatically reset to 0.
Figure 340.
24 23 22
Reserved
8 7 6
TTCM ABOM AWUM
rw rw
RM0090 Rev 18
Controller area network (bxCAN)
21 20 19 18
5 4 3 2
NART RFLM TXFP
rw rw rw rw
17 16
DBF
rw
1 0
SLEEP INRQ
rw rw
1097/1749
1121