Figure 340. Transmit Mailbox States - ST STM32F405 Reference Manual

RM0090
32.7.2 Time triggered communication mode
In this mode, the internal counter of the CAN hardware is activated and used to generate the
Time Stamp value stored in the CAN_RDTxR/CAN_TDTxR registers, respectively (for Rx
and Tx mailboxes). The internal counter is incremented each CAN bit time (refer to
Section 32.7.7). The internal counter is captured on the sample point of the Start Of Frame
bit in both reception and transmission.
32.7.3 Reception handling
For the reception of CAN messages, three mailboxes organized as a FIFO are provided. In
order to save CPU load, simplify the software and guarantee data consistency, the FIFO is
managed completely by hardware. The application accesses the messages stored in the
FIFO through the FIFO output mailbox.
Valid message
A received message is considered as valid when it has been received correctly according to
the CAN protocol (no error until the last but one bit of the EOF field) and It passed through
the identifier filtering successfully, see

Figure 340. Transmit mailbox states

EMPTY
RQCP=X
TXOK=X
TXRQ=1
TME = 1
ABRQ=1
EMPTY
RQCP=1
TXOK=0
TME = 1
Transmit failed * NART
EMPTY
Transmit succeeded
RQCP=1
TXOK=1
TME = 1
RM0090 Rev 18
Controller area network (bxCAN)
PENDING
RQCP=0
TXOK=0
TME = 0
Mailbox does not
have highest priority
ABRQ=1
CAN Bus = IDLE
TRANSMIT
RQCP=0
TXOK=0
TME = 0
Section 32.7.4.
Mailbox has
highest priority
SCHEDULED
RQCP=0
TXOK=0
TME = 0
Transmit failed * NART
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