Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2247

ADSP-SC58x EMAC Register Descriptions
Table 31-76: EMAC_DMA1_BUSMODE Register Fields (Continued)
Bit No.
(Access)
22:17 RPBL
(R/W)
16 FB
(R/W)
13:8 PBL
(R/W)
7 ATDS
(R/W)
31–156
Bit Name
Receive Programmable Burst Length.
The EMAC_DMA1_BUSMODE.RPBL bits indicate the maximum number of beats to
be transferred in one Rx DMA transaction. This is the maximum value that is used in
a single block Read/Write. The Rx DMA always attempts to burst as specified in
RPBL every time it starts a Burst transfer on the host bus. RPBL can be programmed
with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined
behavior. These bits are valid and applicable only when USP is set high.
Fixed Burst.
The EMAC_DMA1_BUSMODE.FB bit controls whether the SCB Master interface
performs fixed burst transfers or not. See the EMAC_DMA0_BMMODE.UNDEF bit de-
scription for more information.
Programmable Burst Length.
The EMAC_DMA1_BUSMODE.PBL bits indicate the maximum number of beats to
be transferred in one DMA transaction. This is the maximum value that is used in a
single block Read/Write. The DMA always attempts to burst as specified in PBL each
time it starts a Burst transfer on the host bus. Any other value results in undefined be-
havior. When USP is set high, this PBL value is applicable for Tx DMA transactions
only.
PBL-max limit = (FIFO size / 2) / 4.
PBL-max limit (transmit) = 256 bytes / 2 /4 = 32.
PBL-max limit (receive) = 128 bytes / 2 /4 = 16.
Note that this PBL is at the DMA end. If PBL= 32 and if BLEN16 is enabled, the
DMA automatically splits 32 bursts in to 2 x 16 bursts. If
EMAC_DMA1_BUSMODE.PBL =8, and if EMAC_DMA0_BMMODE.BLEN16 is ena-
bled, the max burst is limited to EMAC_DMA0_BMMODE.BLEN8. If
EMAC_DMA1_BUSMODE.PBL8 bit is set, the programmed PBL value is multiplied
by 8 times internally. However, the result cannot be more than the above maximum
limits specified above.
Alternate Descriptor Size.
The EMAC_DMA1_BUSMODE.ATDS bit, when set, increases the size of the alternate
descriptor to 32 bytes (8 DWORDS). This is required when the Advanced Time
Stamp feature or Full IPC Offload Engine is enabled in the receiver. When reset, the
descriptor size reverts back to 4 DWORDs (16 bytes). The enhanced descriptor is not
required if the Advanced Time Stamp and IPC Full Checksum Offload features are not
enabled. In such case, you can use the 16 bytes descriptor to save 4 bytes of memory.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration