Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2218

DMA SCB Bus Mode Register
The
EMAC_DMA0_BMMODE
ONEKBBE (R/W)
1K Boundary Crossing Enable
AAL (R)
Address Aligned Beats
BLEN16 (R/W)
SCB Burst Length 16
ENLPI (R/W)
Enable Low Power Interface
WROSRLMT (R/W)
SCB Maximum Write Outstanding Request
Figure 31-28: EMAC_DMA0_BMMODE Register Diagram
Table 31-60: EMAC_DMA0_BMMODE Register Fields
Bit No.
(Access)
31 ENLPI
(R/W)
22:20 WROSRLMT
(R/W)
18:16 RDOSRLMT
(R/W)
13 ONEKBBE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register selects EMAC DMA system cross bar bus mode features.
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
1 1 0 0 0 0 0 0
Bit Name
Enable Low Power Interface.
The EMAC_DMA0_BMMODE.ENLPI bit field's when set to 1, it enable LPI mode
supported by the GMAC configuration and accepts the LPI request from the system
Clock controller.
SCB Maximum Write Outstanding Request.
The EMAC_DMA0_BMMODE.WROSRLMT bit field's value limits the maximum out-
standing request on the SCB write interface. Maximum outstanding requests =
WR_OSR_LMT+1. EMAC-SCB supports up to 4 outstanding write requests.
SCB Maximum Read Outstanding Request.
The EMAC_DMA0_BMMODE.RDOSRLMT bit field's value limits the maximum out-
standing request on the SCB read interface. Maximum outstanding requests =
RD_OSR_LMT+1. EMAC-SCB supports up to 4 outstanding read requests.
1K Boundary Crossing Enable.
When the EMAC_DMA0_BMMODE.ONEKBBE bit is set, the GMAC extensible bus
master performs burst transfers that do not cross 1 KB boundary. When reset, the
GMAC extensible bus master performs burst transfers that do not cross 4 KB boun-
dary.
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1
23 22 21 20 19 18 17 16
0 0 0 1 0 0 0 1
Description/Enumeration
ADSP-SC58x EMAC Register Descriptions
UNDEF (R)
SCB Undefined Burst Length
BLEN4 (R/W)
SCB Burst Length 4
BLEN8 (R/W)
SCB Burst Length 8
RDOSRLMT (R/W)
SCB Maximum Read Outstanding Request
31–127