Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2246

DMA Bus Mode Register
The
EMAC_DMA1_BUSMODE
15
PBL (R/W)
Programmable Burst Length
ATDS (R/W)
Alternate Descriptor Size
31
AAL (R/W)
Address Aligned Bursts
PBL8 (R/W)
PBL * 8
USP (R/W)
Use Separate PBL
Figure 31-44: EMAC_DMA1_BUSMODE Register Diagram
Table 31-76: EMAC_DMA1_BUSMODE Register Fields
Bit No.
(Access)
25 AAL
(R/W)
24 PBL8
(R/W)
23 USP
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register selects the DMA bus operating modes for EMAC DMA.
14 13 12 11 10 9 8
0 0 0 0 0 0 0 1
30 29 28 27 26 25 24 23
0 0 0 0 0 0 0 0
Bit Name
Address Aligned Bursts.
The EMAC_DMA1_BUSMODE.AAL bit, when set high and the FB bit equals 1, di-
rects the SCB interface to generate all bursts aligned to the start address LS bits. If the
FB bit is equal to 0, the first burst (accessing the data buffers start address) is not
aligned, but subsequent bursts are aligned to the address.
PBL * 8.
The EMAC_DMA1_BUSMODE.PBL8 bit, when set high, multiplies the PBL value
programmed (bits [22:17] and bits [13:8]) eight times. Therefore, the DMA transfers
the data in 8, 16, and 32 beats depending on the PBL value.
Use Separate PBL.
The EMAC_DMA1_BUSMODE.USP bit, when set high, configures the Rx DMA to
use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is
applicable to Tx DMA operations only.
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
22 21 20 19 18 17 16
0 0 0 0 0 0 1 0
Description/Enumeration
ADSP-SC58x EMAC Register Descriptions
DSL (R/W)
Descriptor Skip Length
FB (R/W)
Fixed Burst
RPBL (R/W)
Receive Programmable Burst Length
31–155