Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2238

Table 31-71: EMAC_DMA0_STAT Register Fields (Continued)
Bit No.
(Access)
29 TTI
(R/NW)
27 MCI
(R/NW)
26 GLI
(R/NW)
25:23 EB
(R/NW)
22:20 TS
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Time Stamp Trigger Interrupt.
The EMAC_DMA0_STAT.TTI bit indicates an interrupt event in the MAC core's
Time Stamp Generator block. The software must read the corresponding registers in
the MAC core to get the exact cause of interrupt and clear its source to reset this bit to
=0. When this bit is high, the interrupt signal from the MAC is high.
MAC MMC Interrupt.
The EMAC_DMA0_STAT.MCI bit reflects an interrupt event in the MMC module of
the MAC core. The software must read the corresponding registers in the MAC core to
get the exact cause of interrupt and clear the source of interrupt to make this bit as =0.
The interrupt signal from the MAC is high when this bit is high.
Line Interface Interrupt.
The EMAC_DMA0_STAT.GLI bit When set, this bit reflects any of the following in-
terrupt events in the DWC_gmac interfaces
Error Bits.
The EMAC_DMA0_STAT.EB bits indicate the type of error that caused a Bus Error
(for example, error response on the SCB interface). These bits are valid only when the
EMAC_DMA0_STAT.FBI bit is set. This field does not generate an interrupt.
Tx Process State.
The EMAC_DMA0_STAT.TS bits indicate the transmit DMA state. This field does
not generate an interrupt.
ADSP-SC58x EMAC Register Descriptions
Description/Enumeration
0 Error during data buffer access, write transfer, Rx DMA
1 Error during data buffer access, write transfer, Tx DMA
2 Error during data buffer access, read transfer, Rx DMA
3 Error during data buffer access, read transfer, Tx DMA
4 Error during descriptor access, write transfer, Rx DMA
5 Error during descriptor access, write transfer, Tx DMA
6 Error during descriptor access, read transfer, Rx DMA
7 Error during descriptor access, read transfer, Tx DMA
0 Stopped; Reset or Stop Tx Command Issued
1 Running; Fetching Tx Transfer Descriptor
2 Running; Waiting for Status
3 Reading Data from Host Memory Buffer and Queuing
It to Tx Buffer
4 TIME_STAMP Write State
31–147