Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2252

Channel 1 Idle Slope Credit Value Register
The
EMAC_DMA1_CHISC
is present only when you select the Transmit Channel 1 in the AV mode.
Figure 31-48: EMAC_DMA1_CHISC Register Diagram
Table 31-80: EMAC_DMA1_CHISC Register Fields
Bit No.
(Access)
13:0 ISC
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register provides the bandwidth allocated for the AV traffic on Channel 1. This register
15 14 13 12
0 0 0 0
ISC (R/W)
Idle Slope Credit
31 30 29 28
0 0 0 0
Bit Name
Idle Slope Credit.
The EMAC_DMA1_CHISC.ISC bit field contains the idleSlopeCredit value required
for the credit-based shaper algorithm for Channel 1.
11 10 9 8 7 6 5 4
0 0 0 0 0 0 0 0
27 26 25 24 23 22 21 20
0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x EMAC Register Descriptions
3 2 1 0
0 0 0 0
19 18 17 16
0 0 0 0
31–161