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M16C/64C Group
32.19 Notes on Multi-master I
32.19.1 Limitation on CPU Clock
When the CM07 bit in the CM0 register is 1 (CPU clock is a sub clock), do not access the registers
listed in Table 25.4 "Registers". Set the CM07 bit to 0 (main clock, PLL clock, or on-chip oscillator clock)
to access these registers.
32.19.2 Register Access
Refer to the notes below when accessing the I
edge of the first clock of the slave address or 1-byte data transmission/reception to the falling edge of
an ACK clock is considered to be the transmission/reception period. When the ACKCLK bit is 0 (no
ACK clock), the transmission/reception period is from the rising edge of the first clock of the slave
address or 1-byte data transmission/reception to the falling edge of the eighth clock.
32.19.2.1 S00 Register
Do not write to the S00 register during transmission/reception.
32.19.2.2 S1D0 Register
Do not change bits other than the IHR bit in the S1D0 register during transmission/reception.
32.19.2.3 S20 Register
Do not change bits other than the ACKBIT bit in the S20 register during transmission/reception.
32.19.2.4 S3D0 Register
• Do not use the bit managing instruction (read-modify-write instruction) to access the S3D0 register.
Use the MOV instruction to write to this register.
• Rewrite bits ICK1 and ICK0 when the ES0 bit in the S1D0 register is 0 (I
32.19.2.5 S4D0 Register
Rewrite bits ICK4 to ICK2 when the ES0 bit in the S1D0 register is 0 (I
32.19.2.6 S10 Register
•
Do not use the bit managing instruction (read-modify-write instruction) to access the S10 register.
Use the MOV instruction to write to this register.
•
Do not write to the S10 register when bits MST and TRX change their values.
Refer to operation examples in 25.3 "Operations" for bits MST and TRX change.
32.19.3 Low/High-level Input Voltage and Low-level Output Voltage
The low-level input voltage, high-level input voltage, and low-level output voltage differ from the I
specification.
Refer to the recommended operating conditions for I/O ports which share the pins with SCL and SDA.
2
I
C-bus specification
High level input voltage (V
Low level input voltage (V
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
2
C-bus Interface
2
C interface control registers. The period from the rising
) = min. 0.7 V
IH
CC
) = max. 0.3 V
IL
CC
32. Usage Notes
2
C interface disabled).
2
C interface disabled).
2
Page 794 of 807
C-bus
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