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M16C/64C Group
IPL
I flag
Address match
Watchdog timer
Oscillator stop/restart detect
Voltage monitor 1
Voltage monitor 2
DBC
NMI
Figure 14.9
Interrupt Priority Select Circuit 2
14.7.9
Multiple Interrupts
The following shows the internal bit states when control has branched to an interrupt routine.
•
I flag = 0 (interrupt disabled)
•
IR bit = 0 (interrupt not requested)
•
Interrupt priority level = IPL
By setting the I flag to 1 (interrupt enabled) in the interrupt routine, an interrupt request with higher
priority than the IPL can be acknowledged.
The interrupt requests not acknowledged because of their low interrupt priority level are kept pending.
When the IPL is restored by the REIT instruction and interrupt priority is resolved against it, the pending
interrupt request is acknowledged if the following condition is met:
Interrupt priority level of pending interrupt request > Restored IPL
INT Interrupt
14.8
The INTi interrupt (i = 0 to 7) is triggered by the edges of external inputs. The edge polarity is selected
using the IFSRi bit in the IFSR register, or the IFSR30 or IFSR31 bit in the IFSR3A register.
INT4 and INT5 each share an interrupt vector and interrupt control register with SI/O3 and SI/O4,
respectively. To use the INT4 interrupt, set the IFSR6 bit in the IFSR register to 1 ( INT4 ). To use the INT5
interrupt, set the IFSR7 bit in the IFSR register to 1 ( INT5 ).
After modifying the IFSR6 or IFSR7 bit, set the corresponding IR bit to 0 (interrupt not requested) before
enabling the interrupt.
To use the INT6 interrupt, set the PCR5 bit in the PCR register to 0 ( INT6 input enabled). To use the INT7
interrupt, set the PCR6 bit in the PCR register to 0 ( INT7 input enabled).
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
(A)
Determine and output interrupt request level
14. Interrupts
to clock generating circuit
Interrupt request
accepted
Page 216 of 807
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