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M16C/64C Group
Table 6.2
Classification of SFRs Which are Reset
SFR
SFR (A)
Bits OSDR and CWR in the RSTFR register
CWR bit in the RSTFR register
Registers VCR1, VCR2, and VW0C
SFR (B)
Bits VW1C2 and VW1C3 in the VW1C register
Bits VW2C2 and VW2C3 in the VW2C register
Bits PM00 and PM01 in the PM0 register
SFR (C)
VD1LS register
SFR (D)
Bits CM20, CM21, and CM27 in the CM2 register
Table 6.3
I/O Pins
Pin
RESET
VCC1
XIN
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
I/O
Input
Hardware reset input
Power input. The power-on reset, voltage monitor 0 reset, voltage monitor
Input
1 reset, and voltage monitor 2 reset are generated by monitoring VCC1.
Main clock input. The oscillator stop detect reset is generated by
Input
monitoring the main clock.
Register and Bit
Function
6. Resets
Page 44 of 807
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