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M16C/64C Group
RXD polarity
RXDi
switching circuit
Clock source selection
CLK1 to CLK0
CKDIR
f1SIO or
00b
Internal
f2SIO
01b
0
f8SIO
10b
f32SIO
1
External
Clock synchronous type
CKPOL
(when internal clock is selected)
CLK
polarity
CLKi
reversing
circuit
CTS/RTS selected
CTSi/
1
RTSi
CRS
0
n: Value set to the UiBRG register
i = 2, 5 to 7
PCLK1
SMD2 to SMD0, CKDIR
CLK1 to CLK0, CKPOL, CRD, CRS : Bits in the UiC0 register
Note:
1. UART2 is N-channel open drain output. CMOS output cannot be selected.
Figure 23.3
Block Diagram of UART2 and UART5 to UART7
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
f1
UART reception
100b, 101b, 110b
1/16
Clock sync type
UiBRG
register
UART transmission
1/(n+1)
1/16
100b, 101b, 110b
Clock sync type
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when external clock is selected)
CTS/RTS disabled
CTS/RTS disabled
0
1
CRD
VSS
: Bit in the PCLKR register
: Bits in the UiMR register
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
PCLK1
f2SIO
0
1/2
1/2
f1SIO
1
1/8
1/4
SMD2 to SMD0
Reception
control circuit
001b, 010b
Transmission
control circuit
001b, 010b
0
1
CKDIR
RTSi
CTSi
f1SIO or f2SIO
f8SIO
f32SIO
TXD
polarity
switching
circuit
(1)
Receive
Transmit/
clock
receive
unit
Transmit
clock
Page 453 of 807
TXDi
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