Table of Contents
Advertisement
M16C/64C Group
18.3.2
Timer Mode
In timer mode, the timer counts an internally generated count source. Table 18.5 lists Timer Mode
Specifications, Table 18.6 lists Registers and Setting in Timer Mode, and Figure 18.4 shows an
Operation Example in Timer Mode.
Table 18.5
Timer Mode Specifications
Item
Count sources
Count operations
Counter cycles
Count start condition
Count stop condition
Interrupt request
generation timing
TBiIN pin function
Read from timer
Write to timer
i = 0 to 5
TBiS: Bit in the TABSR or TBSR register
Table 18.6
Registers and Settings in Timer Mode
Register
PCLKR
CPSRF
PCLKSTP1
TBi1
PPWFS1 to
PPWFS2
TBCS0 to TBCS3
TABSR
TBSR
TBi
TBiMR
i = 0 to 5
Note:
1.
This table does not describe a procedure.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-S, fC32
•
Decrement
•
When the timer underflows, it reloads the reload register value and continues
counting.
1
----------------- -
(
)
n
+
1
n: setting value of the TBi register
Set the TBiS bit to 1 (start counting).
Set the TBiS bit to 0 (stop counting).
Timer underflow
I/O port
Count value can be read by reading the TBi register.
•
When not counting
The value written to the TBi register is written to both the reload register and the
counter.
•
When counting
The value written to the TBi register is only written to the reload register
(transferred to the counter when reloaded next).
Bit
PCLK0
Select the count source.
CPSR
Write 1 to reset the clock prescaler.
PCKSTP11
Set to 0 when using f1 or main clock.
PCKSTP17
Select the count source.
15 to 0
- (setting unnecessary)
PPWFS12 to
PPWFS10
Set to 0.
PPWFS22 to
PPWFS20
7 to 0
Select the count source.
Set to 1 when starting counting.
TBiS
Set to 0 when stopping counting.
15 to 0
Set the count value.
7 to 0
Refer to the TBiMR register below.
Specification
0000h to FFFFh
(1)
Function and Setting
18. Timer B
Page 315 of 807
Advertisement
Table of Contents
