Cec Function Control Register 2 (Cecc2) - Renesas M16C/64C User Manual

M16C/64C Group
26.2.2

CEC Function Control Register 2 (CECC2)

CEC Function Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Do not write to the CECC2 register while transmitting/receiving.
CTNACK (Transmit NACK (ACK) end select bit) (b1)
This bit is enabled when the CTACKEN bit is set to 1 (end with NACK/ACK).
CTACKEN (Transmit NACK (ACK) end control bit) (b2)
Select the end condition by using the CTNACK bit when the CTACKEN bit is 1 (end with NACK/ACK).
CRACK (ACK output control bit) (b3)
When the CRACK bit is set 0 (inserted by program), the value of the CCRBAO bit in the CCRB2
register is output as ACK data.
When the CRACK bit is set to 1 (inserted by hardware), ACK is output if the received Destination
address matches the address selected by the CRADRI1 or CRADRI2 register. Table 26.5 lists ACK
Output When Inserted by Hardware.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Symbol
CECC2
Bit Symbol Bit Name
Receive edge detection
CRRNG
select bit
Transmit NACK (ACK) end
CTNACK
select bit
Transmit NACK (ACK) end
CTACKEN
control bit
CRACK ACK output control bit
Arbitration lost detect
CTABTS
condition select bit
CFIL Digital filter enable bit
Start bit acceptable range
CSTRRNG
select bit
Data bit acceptable range
CDATRNG
select bit
26. Consumer Electronics Control (CEC) Function
Address
0351h
Function
0: Detects falling edge acceptable
range
1: Detects both edges acceptable
range
0: End with ACK
1: End with NACK
0: Continue transmitting
1: End with NACK/ACK
0: Inserted by program
1: Inserted by hardware
0: When transmitting start bit and
Initiator address
1: When transmitting start bit and all
data bits
0: Filter disabled
1: Filter enabled
0: ±200 µs
1: ±300 µs
0: Period between falling edge and
rising edge ± 200 µs
Period between falling edge and
falling edge ± 350 µs
1: Period between falling edge and
rising edge ± 300 µs
Period between falling edge and
falling edge ± 500 µs
Reset Value
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW
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