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M16C/64C Group
Count source
Count starts with a maximum of a 1.5
cycle delay of the count source after an
external trigger.
n
Count
operations
0000h
TAiS bit in the
TABSR register
TAiIN input
Low-level output
at count stop
TAiOUT output
POFSi = 0
POFSi = 1
High-level output
at count stop
IR bit in the
TAiIC register
i = 0 to 4
POFSi : Bits in the TAPOFS register
The above timing diagram assumes the following:
- The MR0 bit in the TAiMR register
- The MR1 bit in the TAiMR register
- The MR2 bit in the TAiMR register
- Bits TAiTGH to TAiTGL in the ONSF or TRGSR register = 00b
- The TAi register (n) value
Figure 17.10 Operation Example in One-Shot Timer Mode
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Reload and stop
n
counting when
0000h is set.
Trigger
Low-level output
at count stop
High-level
High-level output at count stop
output
at count start
Interrupt request at the falling edge
of TAiOUT when POFSi is 0
Low-level output
Interrupt request at the rising edge
at count start
of TAiOUT when POFSi is 1
Becomes 0 by accepting an interrupt request, or by a program.
Reload
After retrigger,
n+1
Retrigger
while counting
= 1 (pulse output)
= 1
(The rising edge of the TAiIN pin input is the trigger.)
= 1
= 0005h
17. Timer A
Reload and
stop counting
Low-level output
at count stop
High-level output
at count stop
One cycle of
the CPU clock
Page 286 of 807
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