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M16C/64C Group
Memory Expansion Mode and Microprocessor Mode
(in 1 to 3 waits setting and when accessing external area)
Read timing
BCLK
CSi
ADi
BHE
ALE
RD
DBi
Write timing
BCLK
CSi
ADi
BHE
ALE
WR, WRL,
WRH
DBi
1
t
=
cyc
f
(BCLK)
Measuring conditions
V
= V
CC1
CC2
Input timing voltage: V = 0.6 V, V
Output timing voltage: V = 1.5 V, V
Figure 31.29 Timing Diagram
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
t
d(BCLK-CS)
30ns(max.)
t
cyc
t
d(BCLK-AD)
30ns(max.)
t
d(BCLK-ALE)
t
h(BCLK-ALE)
25ns(max.)
-4ns(min.)
t
d(BCLK-RD)
30ns(max.)
t
ac2(RD-DB)
{(n+0.5) × t
Hi-Z
t
d(BCLK-CS)
30ns(max.)
t
cyc
t
d(BCLK-AD)
30ns(max.)
t
t
d(BCLK-ALE)
h(BCLK-ALE)
25ns(max.)
-4ns(min.)
t
d(BCLK-WR)
30ns(max.)
Hi-Z
{(n-0.5) × t
= 3V
= 2.4 V
IL
IH
= 1.5 V
OL
OH
t
h(BCLK-CS)
0ns(min.)
t
h(BCLK-AD)
0ns(min.)
t
h(RD-AD)
0ns(min.)
t
h(BCLK-RD)
0ns(min.)
-60}ns(max.)
cyc
t
su(DB-RD)
60ns(min.)
t
h(BCLK-CS)
0ns(min.)
t
h(BCLK-AD)
0ns(min.)
t
h(WR-AD)
(0.5 × t
-15)ns(min.)
cyc
t
h(BCLK-WR)
0ns(min.)
t
d(BCLK-DB)
40ns(max.)
t
t
d(DB-WR)
h(WR-DB)
-40}ns(min.)
(0.5 × t
-25)ns(min.)
cyc
cyc
n: 1 (when 1 wait)
2 (when 2 waits)
3 (when 3 waits)
31. Electrical Characteristics
V
= V
CC1
CC2
t
h(RD-DB)
0ns(min.)
Page 755 of 807
= 3V
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