Peripheral Clock Stop Register 1 (Pclkstp1) - Renesas M16C/64C User Manual

M16C/64C Group
18.2.3

Peripheral Clock Stop Register 1 (PCLKSTP1)

Peripheral Clock Stop Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register
PCKSTP11 (Timer peripheral clock stop bit) (b1)
When using f1 or the main clock for the timer A and timer B count source, set the PCKSTP11 bit to 0 (f1
provide enabled).
To change the PCKSTP11 bit from 1 (f1 provide disabled) to 0, use following procedure:
(1) Stop timer A and timer B.
(2) Set the PCKSTP11 bit to 0.
(3) Set the registers for timer A and timer B again.
PCKSTP17 (Timer clock source select bit) (b7)
Change the PCKSTP17 bit when all of the following conditions are met:
•
Both f1 and the main clock are stably supplied.
•
Both timer A and timer B are stopped.
The PCKSTP17 bit is used for supplying the main clock to timer A and timer B.
When in PLL operating mode, high-speed mode, medium-speed mode, or wait mode, the main clock
can be used for the timer A and timer B count source.
Do not use the main clock for the timer A and timer B count source in other normal operating modes
(refer to 9.3 "Clock").
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Symbol
PCLKSTP1
Bit Symbol Bit Name
Peripheral clock stop bit
PCKSTP1A
(other than timer A, timer B)
Timer peripheral clock stop bit
PCKSTP11
(timer A, timer B)
—
No register bit. If necessary, set to 0. The read value is undefined.
(b6-b2)
Timer clock source select bit
PCKSTP17
(timer A, timer B)
Address
0016h
Function
0: f1 provide enabled
1: f1 provide disabled
0: f1 provide enabled
1: f1 provide disabled
0: f1
1: Main clock
18. Timer B
Reset Value
0XXX XX00b
RW
RW
RW
—
RW
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