Renesas M16C/64C User Manual page 608

M16C/64C Group
25.3.10.3 Master Reception
Master reception is described in this section. The initial settings described in 25.3.10.1 "Initial
Settings" are assumed to be completed. Figure 25.18 shows the operation example of master
reception. The following programs (A) to (D) are executed at (A) to (D) in Figure 25.18, respectively.
SCLMM
SDAMM
IR bit in the IICIC
register
Figure 25.18 Example of Master Reception
(A) Slave address transmission
(1) The BB bit in the S10 register must be 0 (bus free).
(2) Write E0h to the S10 register (start condition standby).
(3) Write a slave address to the upper 7 bits and a set the least significant bit (LSB) to 1. (Start
condition generated, then slave address transmitted)
(B) Data reception 1 (after slave address transmission)
2
(In I C-bus interrupt routine)
(1) Write AFh to the S10 register (master receive mode).
(2) Set the ACKBIT bit in the S20 register to 0 (ACK presents) because the data is not the last one.
(3) Write dummy data to the S00 register
(C) Data reception 2 (data reception)
2
(In I C-bus interrupt routine)
(1) Read the received data from the S00 register.
(2) Set the ACKBIT bit in the S20 register to 1 (no ACK) because the data is the last one.
(3) Write dummy data to the S00 register.
(D) Completion of master reception
2
(In I C-bus interrupt routine)
(1) Read the received data from the S00 register.
(2) Write C0h to the S10 register (stop condition standby state).
(3) Write dummy data to the S00 register (stop condition generated).
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
S: Start condition
P: Stop condition
m
Slave address
S R
(7 bits)
(A) Slave address transmission
A: ACK R: Read
A: NACK W: Write
s m
Data
A A
(8 bits)
Set to 0 by interrupt request acceptance or by program
(B) Data reception 1
(D) Completion of master reception
25. Multi-master I
m: Master outputs to SDA
s: Slave outputs to SDA
s
Data
A
(8 bits)
(C) Data reception 2
Stop condition
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2
C-bus Interface
m
P