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M16C/64C Group
Example 1
Accessing the external area indicated by CSj in the next cycle
after accessing the external area indicated by CSi.
The address bus and chip select signal both change state
between these two cycles.
Access to the external
area indicated by CSi
BCLK
Read signal
Data bus
Address bus
CSi
CSj
Example 3
Accessing the external area indicated by CSi in the next cycle
after accessing the external area indicated by the same CSi.
The address bus changes state, but the chip select signal
does not.
Access to the external
area indicated by CSi
BCLK
Read signal
Data bus
Address bus
CSi
Note:
1. These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip
select bus cycle may be extended to more than two cycles depending on the combination of these examples.
The figure above assume a separate bus is selected and the area is accessed for read without wait states.
i = 0 to 3, j = 0 to 3 (not including i ≠ j, however)
Examples of Address Bus and CSi Signal Output in 1-MB Mode
Figure 11.2
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Access to the external
area indicated by CSj
Data
Data
Address
Address
Access to the same
external area
Data
Data
Address
Address
Example 2
Accessing the internal ROM or internal RAM in the next cycle
after accessing the external area indicated by CSi.
The chip select signal changes state, but the address bus
does not.
Access to the external
area indicated by CSi
BCLK
Read signal
Data bus
Address bus
CSi
Example 4
Not accessing any area (no instruction prefetch generated) in the
next cycle after accessing the external area indicated by CSi.
Neither the address bus nor the chip select signal changes state
between these two cycles.
Access to the external
area indicated by CSi
BCLK
Read signal
Data bus
Address bus
CSi
11. Bus
Access to the internal
ROM or internal RAM
Data
Address
No access
Data
Address
Page 145 of 807
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