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M16C/64C Group
(1) SWC bit function
SDAi (master)
SCLi (master)
SDAi (slave)
SCLi (slave)
(2) SWC9 bit function
SDAi (master)
SCLi (master)
SDAi (slave)
SCLi (slave)
i = 0 to 2, 5 to 7
Figure 23.24 Inserting Wait-States Using Bits SWC and SWC9
The CSC bit in the UiSMR2 register synchronizes an internally generated clock with the clock applied to
the SCLi pin. For example, if a wait-state is inserted from other devices, the two clocks are not
synchronized. While the CSC bit is 1 (clock synchronization enabled) and the internal clock is held high,
when a high at the SCLi pin changes to low, the internal clock becomes low in order to reload the
UiBRG register value and resume counting. While the SCLi pin is held low, when the internal clock
changes from low to high, the count is stopped until the SCLi pin becomes high. That is, the UARTi
transmit/receive clock is the logical AND of the internal clock and SCLi. The synchronized period starts
from one clock prior to an internally generated clock and ends when the ninth clock is completed. The
CSC bit can be set to 1 only when the CKDIR bit in the UiMR register is set to 0 (internal clock
selected).
The SCLHI bit in the UiSMR4 register is used to leave the SCLi pin open when another master
generates a stop condition while the master is performing a transmit/receive operation. While the
SCLHI bit is set to 1 (output stopped), the SCLi pin is open (the pin is high-impedance) when a stop
condition is detected and the clock output is stopped.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
1
2
3
4
1
2
3
4
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
5
6
7
8
Address bit comparison, acknowledge generation
Clock line is
held low
5
6
7
8
Clock line is
held low
9
A/A
Clock line is
released
(SWC = 0)
A/A
9
Acknowledge check
Clock line is
released
(SWC9 = 0)
Page 498 of 807
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