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M16C/64C Group
32.17.3.3 Low/High-level Input Voltage and Low-level Output Voltage
The low-level input voltage, high-level input voltage, and low-level output voltage differ from the I
bus specification.
Refer to the recommended operating conditions for I/O ports which share the pins with SCL and
SDA.
2
I
C-bus specification
High level input voltage (V
Low level input voltage (V
32.17.3.4 Setup and Hold Times When Generating a Start/Stop Condition
When generating a start condition, the hold time (t
generating a stop condition, the setup time (t
When the SDA digital delay function is enabled, take delay time into consideration (see 23.3.3.7
"SDA Digital Delay").
The following shows a calculation example of hold and setup times when generating a start/stop
condition.
Calculation example when setting 100 kbps
•
UiBRG count source: f1 = 20 MHz
•
UiBRG register setting value: n = 100 - 1
•
SDA digital delay setting value: DL2 to DL0 are 101b (5 or 6 cycles of UiBRG count source)
(theoretical value) = f1 / (2(n+1)) = 20 MHz / (2 × (99 + 1)) = 100 kbps
f
SCL
= delay cycle count / f1 = 6 / 20 MHz = 0.3 μ s
t
DL
t
(theoretical value) = 1 / (2f
HD:STA
t
(theoretical value) = 1 / (2f
SU:STO
f
(actual value) = t
HD:STA
f
(actual value) = t
SU:STO
Internal clock
(UiBRG output)
SCL
SDA
f
: SCL clock
SCL
t
: SDA digital delay time
DL
t
: Hold time when generating a start condition
HD:STA
t
: Set-up time when generating a stop condition
SU:STO
Figure 32.11 Setup and Hold Times When Generating Start and Stop Conditions
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
) = min. 0.7 V
IH
) = max. 0.3 V
IL
(theoretical value)) = 1 / (2 × 100 kbps) = 5 μ s
SCL
(theoretical value)) = 1 / (2 × 100 kbps) = 5 μ s
SCL
(theoretical value) - t
HD:STA
(theoretical value) + t
SU:STO
1 / f
(theoretical value)
SCL
1 / (2f
(theoretical value))
SCL
t
HD:STA
(theoretical value)
t
HD:STA
(actual value)
t
DL
CC
CC
:STA) is a half cycle of the SCL clock. When
HD
:STO) is a half cycle of the SCL clock.
SU
= 5 μ s - 0.3 μ s = 4.7 μ s
DL
= 5 μ s + 0.3 μ s = 5.3 μ s
DL
1 / (2f
32. Usage Notes
(theoretical value))
SCL
t
SU:STO
(theoretical value)
t
SU:STO
(actual value)
t
DL
Page 791 of 807
2
C-
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