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M16C/64C Group
14.13.7 INT Interrupt
•
Either a low level of at least tw(INL) width or a high level of at least tw(INH) width is necessary for
the signal input to pins INT0 through INT7 , regardless of the CPU operation clock.
•
If the POL bit in registers INT0IC to INT7IC, bits IFSR7 to IFSR0 in the IFSR register, or bits
IFSR31 to IFSR30 in the IFSR3A register are changed, the IR bit may inadvertently become 1
(interrupt requested). Be sure to set the IR bit to 0 (interrupt not requested) after changing any of
these register bits.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
14. Interrupts
Page 223 of 807
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