Renesas M16C/64C User Manual page 434

M16C/64C Group
PWMENi bit in the
PWMCON1 register
PWMi prescaler
prelatch
PWMi register prelatch
PWMi prescaler latch
PWMi register
latch
PWMi output
i: 0, 1
fj: PWM count source frequency
The above diagram assumes the PWMPORTi bit in the PWMCON1 register is set to 1 (PWMi output).
Figure 21.3 PWMi Output Example (Duty 0%, Duty 100%)
PWMENi bit in the
PWMCON1 register
PWMi prescaler
prelatch
PWMi register
prelatch
PWMi prescaler latch
PWMi register latch
PWMi output
e.g.1
e.g.2
i: 0, 1
fj: PWM count source frequency
The diagram assumes when the PWMPORTi bit in the PWMCON1 register is 1 (PWMi output).
Figure 21.4 PWMi Output Example (PWM Output Disabled and PWM Output Resumed)
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
1
m
Set the PWMREGi register by a program
n 00h
m
n
(m+1) × n Low level is output in this cycle
fj
when PWMi register latch is 00h
-1) × (m+1)
8
(2
fj
PWMPREi register remains unchanged and PWM cycle is constant.
Change by a program
PWMi output disabled
m1
n1
m1
n1
(m1+1) × n1
fj
-1) × (m1+1)
8
(2
fj
Maintain output level of when
PWMi output is disabled
(m1+1) × n1
fj
-1) × (m1+1)
8
(2
fj
n FFh
00h n
High level is output in this cycle
when PWMi register latch is FFh
m2
Set registers PWMPREi and PWMREGi by a program.
n2
Rewritten value is reflected in second cycle of PWM output
(m1+1) × n1
fj
-1) × (m1+1)
8
(2
fj
PWMi outputs with value before the PWMi output is
disabled for first cycle after PWMi output is enabled
21. Pulse Width Modulator
n
FFh n
m2
n2
(m2+1) × n2
fj
-1) × (m2+1)
8
(2
fj
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