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M16C/64C Group
Memory Expansion Mode and Microprocessor Mode
(Effective in wait state setting)
BCLK
RD
(Separate bus)
WR , WRL , WRH
(Separate bus)
RD
(Multiplexed bus)
WR , WRL , WRH
(Multiplexed bus)
RDY input
Measuring conditions
V
= V
= 3 V
CC1
CC2
Input timing voltage: V = 0.6 V, V
Output timing voltage: V = 1.5 V, V
Figure 31.26 Timing Diagram
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
t
su(RDY-BCLK)
= 2.4 V
IL
IH
= 1.5 V
OL
OH
31. Electrical Characteristics
V
= V
= 3 V
CC1
CC2
t
h(BCLK-RDY)
Page 750 of 807
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