External Clock; Souti Pin - Renesas M16C/64C User Manual

M16C/64C Group
24.3.6

External Clock

When the SMi6 bit in the SiC register is 0, data is transmitted/received using the external clock.
The external clock is used as a transmit/receive clock, the SOUTi output level from when the SMi3 bit in
the SiC register is set to 1 (SI/Oi enabled) and SMi2 bit is set to 0 (SOUTi output enabled) to when the
first data is output can be selected by the SMi7 bit in the SiC register. Refer to 24.3.8 "Function for
Setting SOUTi Initial Value".
Transmission/reception starts with the external clock after writing the transmit data to the SiTRR
register.
Data written to the SiTRR register shifts each time the external clock is input. When completing data
transmission/reception of the eighth bit, read or write to the SiTRR register before inputting the clock for
the next data transmission/reception.
Figure 24.6 shows SI/Oi Operation Timing (External Clock).
If the SMi4 bit is 0, write to the SiTRR register
when CLKi input is high.
CLKi input
Write signal to the
SiTRR register
SOUTi output
SINi input
IR bit in the SiIC
register
i = 3, 4
The above diagram assumes the following:
In the SiC register, SMi2 = 0 (SOUTi output), SMi3 = 1 (SOUTi output, CLKi function), SMi4 = 0 (transmit data is
output at falling edge of transmit/receive clock and receive data is input at rising edge), SMi5 = 0 (LSB first), SMi6 = 0
(external clock)
Figure 24.6 SI/Oi Operation Timing (External Clock)
When the SMi6 bit in the SiC register is 0 (external clock), write to the SiTRR register and SMi7 bit in
the SiC register under the following conditions:
•
When the SMi4 bit in the SiC register is 0 (transmit data is output at falling edge of transmit/receive
clock and receive data is input at rising edge): CLKi input is high.
•
When the SMi4 bit is 1 (transmit data is output at rising edge of transmit/receive clock and receive
data is input at falling edge): CLKi input is low.
24.3.7

SOUTi Pin

The SOUTi pin state can be selected by setting bits SMi2 and SMi3 in the SiC register.
Table 24.4 lists SOUTi Pin State.
Table 24.4 SOUTi Pin State
Bit Setting
SiC register
SMi2 SMi3
0
1
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
D0
D0
SOUTi Pin State
0 I/O port or other peripheral function
1 SOUTi output
0/1 High-impedance
D1 D2 D3
D1 D3
D2
24. Serial Interface SI/O3 and SI/O4
D4 D5 D6
D4 D5 D6
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D7
D7