Renesas M16C/64C User Manual page 114

M16C/64C Group
When the VW2C1 bit
is 0 (digital filter
enabled)
When the VW2C1 bit
is 1 (digital filter
disabled) and the
VW2C7 bit is 0 (when
VCC1 reaches Vdet2
or above)
When the VW2C1 bit
is 1 (digital filter
disabled) and the
VW2C7 bit is 1 (when
VCC1 reaches Vdet2
or below)
VC13: Bit in the VCR1 register
VW2C1, VW2C2, VW2C6, VW2C7: Bits in the VW2C register
The above diagram assumes the following:
• The VC27 bit in the VCR2 register is 1 (voltage detector 2 enabled).
• The VW2C0 bit in the VW2C register is 1 (voltage monitor 2 interrupt/reset enabled).
Note:
1. When not using the voltage monitor 0 reset, operate at recommended operating condition VCC1.
Figure 7.8 Voltage Monitor 2 Interrupt/Reset Operation Example
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
VCC1
Vdet2
VC13 bit
Digital filter sampling clock × 3 cycles Digital filter sampling clock × 3 cycles
VW2C2 bit
Voltage monitor 2
interrupt request
(when VW2C6 is 0)
Internal reset signal
(when VW2C6 is 1)
VW2C2 bit
Voltage monitor 2
interrupt request
(when VW2C6 is 0)
VW2C2 bit
Voltage monitor 2
interrupt request
(when VW2C6 is 0)
Internal reset signal
(when VW2C6 is 1)
Becomes 0 by accepting
an interrupt request
Set to 0
Becomes 0 by accepting an
interrupt request
tps + × 60 cycles (maximum)
8
fOCO-S
7. Voltage Detector
Set to 0
Set to 0
Becomes 0 by accepting
an interrupt request
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