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M16C/64C Group
When the CABTWEN bit is 0:
Low pulse is immediately output regardless of the CEC signal state.
CEC
When the CABTWEN bit is 1:
Low pulse is output at the rising edge of the CEC signal.
CEC
CEC
The above diagram applies under the following condition.
The CABTEN bit in the CECC4 register is 1 (low pulse output enabled in receive error).
CABTWEN: Bit in the CECC4 register
Figure 26.8
Low Pulse Output in Receive Error
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Receive error occurs
3.6 ms
3 to 4 cycles of
the count source
Receive error occurs
3.6 ms
3 to 4 cycles of
count source
26. Consumer Electronics Control (CEC) Function
Low pulse is output at the rising
edge within 3.6 ms after the receive
error occurs.
3.6 ms
If the low level lasts for 3.6 ms
or longer after the receive error
occurs, low pulse is not output
even if the rising edge is
detected thereafter.
Page 603 of 807
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