Renesas M16C/64C User Manual page 485

M16C/64C Group
RXD polarity
RXD1
switching circuit
Clock source selection
CLK1 to CLK0
f1SIO or
00b
f2SIO
01b
0
f8SIO
10b
f32SIO
1
CKPOL
CLK
polarity
CLK1
reversing
circuit
Clock output
pin select
CTS1/RTS1/
CTS0/CLKS1
n: Value set to the U1BRG register
PCLK1
SMD2 to SMD0, CKDIR
CLK1 to CLK0, CKPOL, CRD, CRS : Bits in the U1C0 register
CLKMD0, CLKMD1, RCSP
Figure 23.2 UART1 Block Diagram
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
f1
UART reception
1/16
CKDIR
Internal U1BRG
UART transmission
register
1/(n+1)
1/16
External
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CLKMD0
0
1
CTS/RTS selected
1
CTS/RTS disabled
CRS
1
0
CLKMD1
0
CTS/RTS disabled
0
1
CRD
VSS
: Bit in the PCLKR register
: Bits in the U1MR register
: Bits in the UCON register
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
PCLK1
f2SIO
0
1/2 1/2
f1SIO
1
1/8
SMD2 to SMD0
100b, 101b, 110b
Reception
Clock sync type
control circuit
001b, 010b
100b, 101b, 110b
Transmission
Clock sync type
control circuit
001b, 010b
0
1
CKDIR
RTS1
CTS1
0
1
to CTS0 in UART0
RCSP
f1SIO or f2SIO
f8SIO
1/4
f32SIO
Receive
Transmit/
clock
receive
unit
Transmit
clock
Page 452 of 807
TXD1
TXD
polarity
switching
circuit