17. Timer A; Introduction - Renesas M16C/64C User Manual

M16C/64C Group

17. Timer A

17.1

Introduction

Timers A consists of timers A0 to A4. Each timer operates independently of the others. Table 17.1 lists
Timer A Specifications, Table 17.2 lists Differences in Timer A Mode, Figure 17.1 shows Timer A and B
Count Sources, Figure 17.2 shows Timer A Configuration, Figure 17.3 shows Timer A Block Diagram, and
Table 17.3 lists I/O Ports.
Table 17.1 Timer A Specifications
Item
Configuration 16-bit timer × 5
Operating modes
Interrupt sources Overflow/underflow × 5
Table 17.2 Differences in Timer A Mode
Event counter mode (two-phase pulse signal processing)
Programmable output mode
Clock Generator
Main clock
Main clock
oscillator or
PLL frequency
synthesizer
125 kHz
fOCO-S
on-chip
oscillator
Sub clock
fC
oscillator
Set the CPSR bit in the CPSRF
register to 1 (prescaler reset).
Figure 17.1 Timer A and B Count Sources
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
•
Timer mode
The timer counts an internal count source.
•
Event counter mode
The timer counts pulses from an external device, or overflows and underflows of other timers.
•
One-shot timer mode
The timer outputs a single pulse before it reaches the count 0000h.
•
Pulse width modulation mode (PWM mode)
The timer outputs pulses of given width and cycle successively.
•
Programmable output mode
The timer outputs a given pulse width of a high/low level signal (timers A1, A2, and A4).
Item
PCKSTP17
CM21
0
1
f1
0
1
fOCO-S
fC32
1/32
Reset
Specification
A0
No
No
PCKSTP11
f1/main clock
CM21: Bit in the CM2 register
PCLK0: Bit in the PCLKR register
PCKSTP17, PCKSTP11: Bit in the PCLKSTP1 register
Timer
A1 A2 A3
No Yes Yes
Yes Yes No
PCLK0
f1TIMAB
1
f2TIMAB
1/2
0
1/8
1/4
1/2
Timer AB divider
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17. Timer A
A4
Yes
Yes
f1TIMAB
or
f2TIMAB
f8TIMAB
f32TIMAB
f64TIMAB
fOCO-S
fC32