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M16C/64C Group
23.3.3.3
Arbitration
The MCU determines whether the transmit data matches data input to the SDAi pin on the rising edge
of SCLi. If it does not match the input data, arbitration takes place at the SDAi pin by stopping data
output.
The ABC bit in the UiSMR register (i = 0 to 2, 5 to 7) determines the update timing for the ABT bit in the
UiRB register.
When the ABC bit is 0 (update per bit), the ABT bit becomes 1 as soon as a data discrepancy is
detected. If not detected, the ABT bit becomes 0. When the ABC bit is 1 (update per byte), the ABT bit
becomes 1 on the falling edge of the eighth bit of SCLi if any discrepancy is detected. In this ABC bit
setting, the ABT bit should be set to 0 after ACK detection of 1-byte is completed to start the next 1-byte
transmission/reception.
When the ALS bit in the UiSMR2 register is set to 1 (SDA output stop enabled), an arbitration lost
occurs. As soon as the ABT bit becomes 1, the SDAi pin becomes high-impedance.
23.3.3.4
SCL Control and Clock Synchronization
Data transmission/reception in I
"Transfer to UiRB Register and Interrupt Timing". The clock speed increase makes it difficult to secure
the required time for ACK generation and data transmit procedure. The I
wait-state insertion to secure this required time and a function of clock synchronization with a wait-state
inserted by other devices.
The SWC bit in the UiSMR2 register (i = 0 to 2, 5 to 7) is used to insert a wait-state for ACK generation.
When the SWC bit is set to 1 (the SCLi pin is held low after the eighth bit of SCLi is received), the SCLi
pin is held low on the falling edge of the eighth bit of SCLi. When the SWC bit is set to 0 (no wait-
state/wait-state cleared), the SCLi line is released.
When the SWC2 bit in the UiSMR2 register is set to 1 (the SCLi pin is held low), the SCLi pin is forced
low even during transmission or reception. When the SWC2 bit is set to 0 (transmit/receive clock is
output at the SCLi pin), the SCLi line is released to output the transmit/receive clock.
The SWC9 bit in the UiSMR4 register is used to insert a wait-state for checking received acknowledge
bits. While the CKPH bit in the UiSMR3 register is 1 (clock delayed), when the SWC9 bit is set to 1 (the
SCLi pin is held low after the ninth bit of the SCLi is received), the SCLi pin is held low on the falling
edge of the ninth bit of SCLi. When the SWC9 bit is set to 0 (no wait-state/wait-state cleared), the SCLi
line is released.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
2
C mode uses the transmit/receive clock as shown in Figure 23.20
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
2
C mode supports a function of
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