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M16C/64C Group
32.12 Notes on Timer A
32.12.1 Common Notes on Multiple Modes
32.12.1.1 Register Setting
The timer stops after reset. Set the mode, count source, counter value, etc., using registers TAiMR,
TAi, TAi1, UDF, TRGSR, PWMFS, TACS0 to TACS2, TAPOFS, PCLKR, and bits TAZIE, TA0TGL,
and TA0TGH in the ONSF register before setting the TAiS bit in the TABSR register to 1 (count
started) (i = 0 to 4).
Always make sure registers TAiMR, UDF, TRGSR, PWMFS, TACS0 to TACS2, TAPOFS, PCLKR,
and bits TAZIE, TA0TGL, TA0TGH in the ONSF register are modified while the TAiS bit is 0 (count
stopped), regardless of whether after reset or not.
32.12.1.2 Event or Trigger
When bits TAiTGH to TAiTGL in the registers ONSF or TRGSR are 01b, 10b, or 11b, an event or a
trigger occurs when an interrupt request of the selected timer is generated. An event or trigger occurs
while an interrupt is disabled because an interrupt request signal is generated regardless of the I flag,
IPL, or interrupt control registers.
For some modes of the timers selected using bits TAiTGH to TAiTGL, an interrupt request is gener-
ated by a source other than overflow or underflow.
For example, when using pulse-period measurement mode or pulse-width measurement mode in
timer B2, an interrupt request is generated at an active edge of the measurement pulse. For details,
refer to the "Interrupt request generation timing" in each mode's specification table.
32.12.1.3 Influence of SD
When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three-
phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance:
P7_2/CLK2/TA1OUT/V, P7_3/ CTS2 / RTS2 /TA1IN/ V , P7_4/TA2OUT/W,
P7_5/TA2IN/ W , P8_0/TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/ CTS5 / RTS5 / U
32.12.1.4 Main Clock
When using the main clock for the timer A and timer B count source (PCKSTP17 bit in the PCLKSTP1
register is 1), adhere the following:
•
Set the PCKSTP11 bit in the PCLKSTP1 register to 0 (f1 supply enabled).
•
The main clock can be used in PLL operating mode, high-speed mode, medium-speed mode, or
wait mode. Do not use the main clock for the timer A and timer B count source in other modes.
•
When the PCKSTP17 bit is set to 1 and timer A or timer B operates in wait mode, set the CM02 bit
to 0 (peripheral function clock f1 does not stop in wait mode).
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
32. Usage Notes
Page 778 of 807
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