Renesas M16C/64C User Manual page 152

M16C/64C Group
PLL operating mode
High-speed mode
and
medium-speed mode
b, e, f
125 kHz on-chip
oscillator mode
a, f
Figure 9.2 Clock Divide Transition
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
PLL clock
PLL clock
divided by 16
divided by 8
c
Medium-speed mode
Main clock
Main clock
divided by 16
divided by 8
fOCO-S
fOCO-S
divided by 16
divided by 8
PLL clock
divided by 4
b
Main clock
divided by 4
a, c
fOCO-S
divided by 4
When the clock division ratio is switched in 125 kHz on-chip oscillator
mode, there is no limitation.
e
9. Power Control
CPU clock source
PLL clock PLL clock
divided by 2 divided by 1
CPU clock source
High-speed mode
Main clock
Main clock
divided by 2 divided by 1
CPU clock source
fOCO-S fOCO-S
divided by 1
divided by 2
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