14.13.4
14.13.5
14.13.6
INT Interrupt .................................................................................................................... 223
14.13.7
15. Watchdog Timer....................................................................................................... 224
15.1
Introduction ............................................................................................................................... 224
15.2
Registers................................................................................................................................... 225
15.2.1
15.2.2
15.2.3
15.2.4
15.2.5
15.3
15.3.1
15.4
Operations ................................................................................................................................ 230
15.4.1
15.4.2
15.5
Interrupts................................................................................................................................... 232
15.6
16. DMAC ...................................................................................................................... 234
16.1
Introduction ............................................................................................................................... 234
16.2
Registers................................................................................................................................... 236
16.2.1
16.2.2
16.2.3
16.2.4
16.2.5
16.3
Operations ................................................................................................................................ 243
16.3.1
DMA Enabled .................................................................................................................. 243
16.3.2
DMA Request .................................................................................................................. 243
16.3.3
Transfer Cycles ............................................................................................................... 244
16.3.4
DMAC Transfer Cycles .................................................................................................... 246
16.3.5
Single Transfer Mode ...................................................................................................... 247
16.3.6
Repeat Transfer Mode ..................................................................................................... 248
16.3.7
16.4
Interrupts................................................................................................................................... 250
16.5
Notes on DMAC........................................................................................................................ 251
16.5.1
16.5.2
A - 7