Renesas M16C/64C User Manual page 150

M16C/64C Group
Table 9.4 Selecting Clock Division Related Bits
Division
(2)
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
Notes:
1. While in high-speed mode, medium-speed mode, PLL operating mode, 125 kHz on-chip oscillator
mode, or 125 kHz on-chip oscillator low power mode.
2. Select divide-by-1 (no division) in high-speed mode.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
(1)
CM1 Register
Bits CM17 to CM16
00b
01b
10b
−
11b
9. Power Control
CM0 Register
CM06 bit
0
0
0
1
0
−
: Any value from 00b to 11b
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