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M16C/64C Group
25.3.9
Timeout Detection
When the SCL clock is stopped during transmission/reception, each device stops operating, keeping
the communication state. To avoid this, the I
2
generate an I
C-bus interrupt request when the SCLMM pin is driven high for more than the selected
timeout detection period during transmission/reception. Figure 25.16 shows the Timeout Detection
Timing. Refer to "TOSEL (Timeout Detection Period Select Bit) (b2)" in 25.2.8 "I2C0 Control Register 2
(S4D0)" for the timeout detection period.
When the TOE bit in the S4D0 register is 1 (timeout detection enabled):
SCLMM
SDAMM
BB bit
in the S10 register
TOF bit
in the S4D0 register
IR bit
in the IICIC register
Note:
1. Select by the TOSEL bit in the S4D0 register.
Figure 25.16 Timeout Detection Timing
A timeout is detected when all of the following conditions are met:
•
The TOE bit in the S4D0 register is 1 (timeout detection enabled)
•
The BB bit in the S10 register is 1 (bus busy)
•
The SCLMM pin is driven high for more than the timeout detect period
When a timeout is detected:
•
The TOF bit in the S4D0 register becomes 1 (timeout detected)
•
The IR bit in the IICIC register becomes 1 (I
When the timeout is detected, perform one of the following:
•
Set the ES0 bit in the S1D0 register to 0 (disabled).
•
Set the IHR bit in the S1D0 register to 1 (I
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
2
C interface incorporates a function to detect timeouts and
1
2
2
C-bus interrupt requested)
2
C interface reset).
2
25. Multi-master I
C-bus Interface
3
(1)
Timeout period
Set to 0 by interrupt request
acceptance or by a program
Page 572 of 807
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