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11.4.1
Reading Data Flash ......................................................................................................... 153
11.4.2
External Bus .................................................................................................................... 153
11.4.3
External Access Immediately after Writing to the SFRs .................................................. 153
HOLD ............................................................................................................................... 153
11.4.4
12. Memory Space Expansion Function ........................................................................ 154
12.1
Introduction ............................................................................................................................... 154
12.2
Registers................................................................................................................................... 154
12.2.1
Data Bank Register (DBR) .............................................................................................. 155
12.3
Operations ................................................................................................................................ 156
12.3.1
1-MB Mode ...................................................................................................................... 156
12.3.2
4-MB Mode ...................................................................................................................... 158
13. Programmable I/O Ports .......................................................................................... 165
13.1
Introduction ............................................................................................................................... 165
13.2
I/O Ports and Pins..................................................................................................................... 166
13.3
Registers................................................................................................................................... 178
13.3.1
Pull-Up Control Register 0 (PUR0) .................................................................................. 179
13.3.2
Pull-Up Control Register 1 (PUR1) .................................................................................. 180
13.3.3
Pull-Up Control Register 2 (PUR2) .................................................................................. 181
13.3.4
Port Control Register (PCR) ............................................................................................ 182
13.3.5
Port Pi Register (Pi) (i = 0 to 10) ..................................................................................... 183
13.3.6
Port Pi Direction Register (PDi) (i = 0 to 10) .................................................................... 184
NMI / SD Digital Filter Register (NMIDF) ........................................................................... 185
13.3.7
13.4
Peripheral Function I/O............................................................................................................. 186
13.4.1
Peripheral Function I/O and Port Direction Bits ............................................................... 186
13.4.2
Priority Level of Peripheral Function I/O .......................................................................... 186
NMI / SD Digital Filter ........................................................................................................ 187
13.4.3
13.4.4
CNVSS Pin ...................................................................................................................... 187
13.5
Unassigned Pin Handling ......................................................................................................... 188
13.6
Notes on Programmable I/O Ports............................................................................................ 190
Influence of SD ................................................................................................................ 190
13.6.1
13.6.2
Influence of SI/O3 and SI/O4 ........................................................................................... 190
14. Interrupts.................................................................................................................. 191
14.1
Introduction ............................................................................................................................... 191
14.2
Registers................................................................................................................................... 192
14.2.1
Processor Mode Register 2 (PM2) .................................................................................. 194
14.2.2
(TB5IC, TB4IC/U1BCNIC, TB3IC/U0BCNIC, BCNIC, DM0IC to DM3IC, KUPIC, ADIC,
S0TIC to S2TIC, S0RIC to S2RIC, TA0IC to TA4IC, TB0IC to TB2IC, U5BCNIC/CEC1IC,
S5TIC/CEC2IC, S5RIC to S7RIC, U6BCNIC/RTCTIC, S6TIC/RTCCIC,
U7BCNIC/PMC0IC, S7TIC/PMC1IC, IICIC, SCLDAIC) .................................................. 195
A - 5
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