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M16C/64C Group
Memory Expansion Mode and Microprocessor Mode
(in no wait state setting)
Read timing
BCLK
CSi
ADi
BHE
ALE
RD
DBi
Write timing
BCLK
CSi
ADi
BHE
ALE
WR, WRL,
WRH
DBi
t
=
cyc
Measuring conditions
V
CC1
Input timing voltage: V = 0.6 V, V
Output timing voltage: V = 1.5 V, V
Figure 31.28 Timing Diagram
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
t
d(BCLK-CS)
30ns(max.)
t
cyc
t
d(BCLK-AD)
30ns(max.)
t
t
h(BCLK-ALE)
d(BCLK-ALE)
-4ns(min.)
25ns(max.)
t
d(BCLK-RD)
30ns(max.)
t
ac1(RD-DB)
(0.5 × t
-60)ns(max.)
cyc
Hi-Z
t
su(DB-RD)
60ns(min.)
t
d(BCLK-CS)
30ns(max.)
t
cyc
t
d(BCLK-AD)
30ns(max.)
t
t
h(BCLK-ALE)
d(BCLK-ALE)
-4ns(min.)
25ns(max.)
t
d(BCLK-WR)
30ns(max.)
Hi-Z
(0.5 × t
1
f
(BCLK)
= V
= 3V
CC2
IL
IH
OL
t
h(BCLK-CS)
0ns(min.)
t
h(BCLK-AD)
0ns(min.)
t
h(RD-AD)
0ns(min.)
t
h(BCLK-RD)
0ns(min.)
t
h(RD-DB)
0ns(min.)
t
h(BCLK-AD)
0ns(min.)
t
h(WR-AD)
(0.5 × t
-15)ns(min.)
cyc
t
h(BCLK-WR)
0ns(min.)
t
d(BCLK-DB)
40ns(max.)
t
t
d(DB-WR)
h(WR-DB)
-40)ns(min.)
(0.5 × t
-25)ns(min.)
cyc
cyc
= 2.4 V
= 1.5 V
OH
31. Electrical Characteristics
V
= V
CC1
CC2
t
h(BCLK-CS)
0ns(min.)
= 3V
Page 753 of 807
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