Renesas M16C/64C User Manual page 545

M16C/64C Group
Figure 23.36 shows the Example of SIM Interface Connection. Connect pins TXD2 and RXD2, and then
place a pull-up resistance.
Figure 23.36 Example of SIM Interface Connection
23.3.6.1 Parity Error Signal Output
The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to 1 (error signal
output).
The parity error signal is output when a parity error is detected while receiving data. A low-level signal is
output from the TXD2 pin in the timing shown in Figure 23.37. If the U2RB register is read while
outputting a parity error signal, the PER bit is cleared to 0 (no parity error) and at the same time the
TXD2 output again goes high.
When transmitting, a transmission complete interrupt request is generated at the falling edge of the
transmit/receive clock pulse that immediately follows the stop bit. Therefore, whether a parity error
signal has been returned can be determined by reading the port that shares the RXD2 pin in a
transmission complete interrupt routine.
Transmit/receive clock
RI bit in the
U2C1 register
The timing diagram assumes the direct format is implemented.
Note:
Figure 23.37 Parity Error Signal Output Timing
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
MCU
TXD2
RXD2
High
Low
High
RXD2
ST
Low
High
TXD2
Low
1
0
1. MCU output is high-impedance (pulled up externally).
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
SIM card
D0 D1 D2 D3 D4
(NOTE 1)
D5 D6 D7 P SP
ST : Start bit
P : Even parity
SP : Stop bit
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