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23.3
Operations ................................................................................................................................ 471
23.3.1
Clock Synchronous Serial I/O Mode ................................................................................ 471
23.3.2
Clock Asynchronous Serial I/O (UART) Mode ................................................................. 479
23.3.3
23.3.4
Special Mode 2 ............................................................................................................... 503
23.3.5
Special Mode 3 (IE Mode) .............................................................................................. 507
23.3.6
Special Mode 4 (SIM Mode) (UART2) ............................................................................. 509
23.4
Interrupts................................................................................................................................... 514
23.4.1
Interrupt Related Registers .............................................................................................. 514
23.4.2
Reception Interrupt .......................................................................................................... 515
23.5
Notes on Serial Interface UARTi (i = 0 to 2, 5 to 7) .................................................................. 516
23.5.1
Common Notes on Multiple Modes ................................................................................. 516
23.5.2
Clock Synchronous Serial I/O Mode ................................................................................ 516
23.5.3
23.5.4
Special Mode 4 (SIM Mode) ............................................................................................ 519
24. Serial Interface SI/O3 and SI/O4 ............................................................................. 520
24.1
Introduction ............................................................................................................................... 520
24.2
Registers................................................................................................................................... 522
24.2.1
Peripheral Clock Select Register (PCLKR) ..................................................................... 523
24.2.2
SI/Oi Transmit/Receive Register (SiTRR) (i = 3, 4) ......................................................... 523
24.2.3
SI/Oi Control Register (SiC) (i = 3, 4) .............................................................................. 524
24.2.4
SI/Oi Bit Rate Register (SiBRG) (i = 3, 4) ........................................................................ 525
24.2.5
SI/O3, 4 Control Register 2 (S34C2) ............................................................................... 525
24.3
Operations ................................................................................................................................ 526
24.3.1
Basic Operations ............................................................................................................. 526
24.3.2
CLK Polarity Selection ..................................................................................................... 526
24.3.3
LSB First or MSB First Selection ..................................................................................... 527
24.3.4
Internal Clock ................................................................................................................... 528
24.3.5
Function for Selecting SOUTi State after Transmission ................................................... 529
24.3.6
External Clock ................................................................................................................. 530
24.3.7
SOUTi Pin ........................................................................................................................ 530
24.3.8
Function for Setting SOUTi Initial Value .......................................................................... 531
24.4
Interrupt .................................................................................................................................... 532
24.5
Notes on Serial Interface SI/O3 and SI/O4............................................................................... 533
24.5.1
SOUTi Pin Level When SOUTi Output Is Disabled ......................................................... 533
24.5.2
External Clock Control ..................................................................................................... 533
24.5.3
Register Access When Using the External Clock ............................................................ 533
24.5.4
SiTRR Register Access ................................................................................................... 533
24.5.5
Pin Function Switch When Using the Internal Clock ....................................................... 533
24.5.6
Operation after Reset When Selecting the External Clock .............................................. 533
2
C Mode) ............................................................................................. 488
2
C Mode) ............................................................................................. 517
A - 12
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