Renesas M16C/64C User Manual page 522

M16C/64C Group
SDAi
Delay
circuit
ACKC = 1
Noise
filter
SCLi
IICM = 0
IICM = 1
Noise
filter
i = 0 to 2, 5 to 7
This diagram applies when bits SMD2 to SMD0 in the UiMR register are 010b and the IICM bit in the UiSMR register is 1.
IICM: Bit in the UiSMR register
IICM2, SWC, ALS, SWC2, SDHI: Bits in the UiSMR2 register
STSPSEL, ACKD, ACKC: Bits in the UiSMR4 register
Figure 23.18 I 2 C Mode Block Diagram
UiBRG count source
n: UiBRG register setting value
Figure 23.19 Internal Clock Configuration
Table 23.15 I/O Pin Functions in I
Pin Name
(1, 2)
SCLi
(1, 2)
SDAi
Note:
1. Set the port direction bit sharing pin to 0.
Pins CLKi and CTSi / RTSi are not used (they can be used as I/O ports).
2.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
STSPSEL = 1
STSPSEL = 0
ACKC = 0
SDHI
ALS
ACKD bit
D
Q Arbitration
T
Start condition
detection
Stop condition
detection
Falling edge
detection
Port register
R
I/O port
Q
Internal clock
STSPSEL=0
UARTi
STSPSEL
External
= 1
clock
2
C Mode
I/O
I/O
I/O
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Start and stop condition generation block
SDA (STSP)
SCL (STSP)
Transmission
register
UARTi
Reception
register
UARTi
S Bus
Q
busy
R
D
Q
T
D
Q
T
9th bit
SWC2
CLK
control
UARTi
8th bit falling edge
R
S
SWC
UiBRG
1/(n+1) 1/2
Function
Clock input or output
Data input or output
DMA0 to DMA3 request
IICM2 = 1
UARTi transmit, NACKi
interrupt request
IICM = 1 and
IICM2 = 0
DMA0, DMA2 request
IICM2 = 1
UARTi receive,
ACKi interrupt request,
DMA1, DMA3 request
IICM = 1 and
IICM2 = 0
NACK
ACK
Start/stop condition
detection interrupt
request
SCL clock
(internal clock)
Sampling clock of
digital delay circuit
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