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M16C/64C Group
Timer A underflow
PCR4
CEC
CRXDEN
CCLK1, CCLK0: Bits in the CECC1 register
CRRNG, CTNACK, CTACKEN, CRACK, CTABTS, CFIL, CSTRRNG, CDATRNG: Bits in the CECC2 register
CTXDEN, CRXDEN: Bits in the CECC3 register
CRFLG, CTFLG, CRERRFLG, CTABTFLG, CTNACKFLG, CRD8FLG, CTD8FLG : Bits in the CECFLG register
CCTBE, CCTBA: Bits in the CCTB2 register
CCRBE, CCRBAO, CCRBAI: Bits in the CCRB2 register
PCR4: Bit in the PCR register
CCTB1: CCTB1 register
CCRB1: CCRB1 register
CRADRI1, CRADRI2: Registers CRADRI1 and CRADRI2
Figure 26.1
CEC Function Block Diagram
Table 26.3
I/O Pin
Pin Name
CEC
Note:
1.
Set the direction bit of the ports sharing a pin to 0 (input mode).
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
CCLK1 to CCLK0
00b
fC
01b
CTNACK, CTACKEN
CCTB1
CCTBE
CTXDEN
Transmission
circuit
ACK output
CSTRRNG
Start bit
detection
CFIL
0
Digital
1
filter
Arbitration
detection
I/O
Input/Output
CEC input and output (N-channel open drain output)
26. Consumer Electronics Control (CEC) Function
Clock control
circuit
CTFLG
CRACK
0
CCRBAO
1
CRRNG
CDATRNG
0/1
determination
Receiving
circuit
CTABTS
CCRB1
Description
Supply to CEC blocks
(32.768 kHz)
CTD8FLG
Detect transmission
of 8 bits of data
Detect Destination
Address
address match or
comparator
Broadcast
CRADRI1
CRADRI2
CRFLG
CRD8FLG
(Detect reception of
8/10 bits of data)
CTNACKFLG
(Detect NACK in
transmission)
CCTBA
CCRBE
CCRBAI
CRERRFLG
(Receive signals outside
tolerated range)
CTABTFLG
(Detect arbitration lost)
Page 584 of 807
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