Renesas M16C/64C User Manual page 18

22.2.3 PMCi Function Select Register 2 (PMCiCON2) (i = 0, 1) .................................................411
22.2.4 PMCi Function Select Register 3 (PMCiCON3) (i = 0, 1) ................................................ 413
22.2.5 PMCi Status Register (PMCiSTS) (i = 0, 1) ..................................................................... 414
22.2.6 PMCi Interrupt Source Register (PMCiINT) (i = 0, 1) ...................................................... 417
22.2.7 PMCi Header Pattern Set Register (MIN) (PMCiHDPMIN) (i = 0, 1)
PMCi Header Pattern Set Register (MAX) (PMCiHDPMAX) (i = 0, 1) ............................. 418
22.2.8 PMCi Data 0 Pattern Set Register (MIN) (PMCiD0PMIN) (i = 0, 1)
PMCi Data 0 Pattern Set Register (MAX) (PMCiD0PMAX) (i = 0, 1)
PMCi Data 1 Pattern Set Register (MIN) (PMCiD1PMIN) (i = 0, 1)
PMCi Data 1 Pattern Set Register (MAX) (PMCiD1PMAX) (i = 0, 1) .............................. 420
22.2.9 PMCi Measurements Register (PMCiTIM) (i = 0, 1) ........................................................ 421
22.2.10 PMC0 Receive Bit Count Register (PMC0RBIT) ............................................................. 421
22.2.11 PMC0 Receive Data Store Register i (PMC0DATi) (i = 0 to 5) ........................................ 422
22.2.12 PMC0 Compare Control Register (PMC0CPC) ............................................................... 423
22.2.13 PMC0 Compare Data Register (PMC0CPD) ................................................................... 424
22.3 Operations ................................................................................................................................ 425
22.3.1 Common Operations in Multiple Modes .......................................................................... 425
22.3.2 Pattern Match Mode (PMC0 and PMC1 Operate Independently) ................................... 427
22.3.3 Pattern Match Mode (Combined Operation of PMC0 and PMC1) ................................... 433
22.3.4 Input Capture Mode (Operating PMC0 and PMC1 Independently) ................................. 438
22.3.5 Input Capture Mode (Simultaneous Count Operation of PMC0 and PMC1) ................... 442
22.4 Interrupts................................................................................................................................... 445
22.5 Notes on Remote Control Signal Receiver ............................................................................... 448
22.5.1 Starting/Stopping PMCi .................................................................................................... 448
22.5.2 Reading the Register ....................................................................................................... 448
22.5.3 Rewriting the Register ..................................................................................................... 448
22.5.4 Combined Operation ....................................................................................................... 449
23. Serial Interface UARTi (i = 0 to 2, 5 to 7) ................................................................. 450
23.1 Introduction ............................................................................................................................... 450
23.2 Registers................................................................................................................................... 455
23.2.1 Peripheral Clock Select Register (PCLKR) ..................................................................... 457
23.2.2 UARTi Transmit/Receive Mode Register (UiMR) (i = 0 to 2, 5 to 7) ................................ 458
23.2.3 UARTi Bit Rate Register (UiBRG) (i = 0 to 2, 5 to 7) ....................................................... 459
23.2.4 UARTi Transmit Buffer Register (UiTB) (i = 0 to 2, 5 to 7) ............................................... 459
23.2.5 UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 to 2, 5 to 7) ............................ 460
23.2.6 UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 to 2, 5 to 7) ............................ 462
23.2.7 UARTi Receive Buffer Register (UiRB) (i = 0 to 2, 5 to 7) ............................................... 463
23.2.8 UART Transmit/Receive Control Register 2 (UCON) ...................................................... 465
23.2.9 UARTi Special Mode Register 4 (UiSMR4) (i = 0 to 2, 5 to 7) ......................................... 466
23.2.10 UARTi Special Mode Register 3 (UiSMR3) (i = 0 to 2, 5 to 7) ......................................... 468
23.2.11 UARTi Special Mode Register 2 (UiSMR2) (i = 0 to 2, 5 to 7) ......................................... 469
23.2.12 UARTi Special Mode Register (UiSMR) (i = 0 to 2, 5 to 7) .............................................. 470
A - 11