Renesas M16C/64C User Manual page 184

M16C/64C Group
(1) Separate Bus, No Wait States
BCLK
Address
WR , WRL , WRH
(2) Separate Bus, One Wait State (1φ + 1φ)
BCLK
Address
WR , WRL , WRH
(3) Separate Bus, Two Wait States (1φ + 2φ)
BCLK
Address
WR , WRL , WRH
i = 0 to 3
A: Address
Note:
1. When consecutively accessing the same chip-select area, CSi continues outputting a low level.
Figure 11.6 Typical Bus Timings Using Software Wait States (1/2)
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Bus cycle = 2φ
A
CSi
Data
RD
Bus cycle = 2φ
A
CSi
Data
RD
Bus cycle = 3φ
CSi
Data
RD
RD: Read data (input)
Bus cycle = 1φ
A
WD RD
Bus cycle = 2φ
A
WD
A
WD
WD: Write data (output)
(Note 1)
(Note 1)
RD
Bus cycle = 3φ
A
(Note 1)
RD
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11. Bus