18. Timer B; Introduction - Renesas M16C/64C User Manual

M16C/64C Group

18. Timer B

18.1

Introduction

Timer B consists of timers B0 to B5. Each timer operates independently of the others. Table 18.1 lists
Timer B Specifications, Figure 18.1 shows Timer A and B Count Sources, Figure 18.2 shows the Timer B
Configuration, Figure 18.3 shows the Timer B Block Diagram, and Table 18.2 lists the I/O Ports.
Table 18.1 Timer B Specifications
Item
Configuration 16-bit timer × 6
Operating modes
Interrupt source Overflow/underflow/active edge of measurement pulse × 6
Clock Generator
Main clock
Main clock
oscillator or
PLL frequency
synthesizer
125 kHz
fOCO-S
on-chip
oscillator
Sub clock
fC
oscillator
Set the CPSR bit in the CPSRF
register to 1 (prescaler reset).
Figure 18.1 Timer A and B Count Sources
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
•
Timer mode
The timer counts an internal count source.
•
Event counter mode
The timer counts pulses from an external device, or overflows and underflows of other timers.
•
Pulse period/pulse width measurement modes
The timer measures pulse periods or pulse widths of an external signal.
PCKSTP17
CM21
0
1
f1
0
1
fOCO-S
fC32
1/32
Reset
Specification
PCKSTP11
f1/main clock
CM21: Bit in the CM2 register
PCLK0: Bit in the PCLKR register
PCKSTP17, PCKSTP11: Bit in the PCLKSTP1 register
PCLK0
f1TIMAB
1
f2TIMAB
1/2
0
1/8
1/4
1/2
Timer AB divider
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18. Timer B
f1TIMAB
or
f2TIMAB
f8TIMAB
f32TIMAB
f64TIMAB
fOCO-S
fC32