Renesas M16C/64C User Manual page 532

M16C/64C Group
(1) Clock synchronization
Clock output
of other device
SCLi
Internal clock
(2) Synchronization period
Internal clock
SCLi
Write of transmit data
i = 0 to 2, 5 to 7
Figure 23.25 Clock Synchronization
23.3.3.5 SCL Clock Frequency
The SCL clock duty generated in I
2
when the I C-bus setting is Fast-mode maximum SCL clock (400 kbps). This value does not satisfy the
2
Fast-mode I C-bus specification (f
satisfy the SCL clock low-level width of 1.3 μ s or more.
When the clock synchronous function (Figure 23.25 "Clock Synchronization") is enabled, there is a
sampling delay of the noise filter plus 1 to 1.5 cycles of UiBRG count source.
There is also a delay of the SCL clock when high is determined and the SCL clock high width is
extended. Therefore, the actual SCL clock becomes slower than SCL clock bit rate setting.
To calculate the effective value of SCL clock, take the SCL clock rise time (t
The following is an example of an SCL clock calculation.
Example of an effective value of SCL clock calculation at 384.6 kbps
•
UiBRG count source: f1 = 20 MHz
•
UiBRG register setting value: n = 26 - 1
•
SCL clock rise time: t
•
SCL clock fall time: t
•
Noise filter width: t
•
Sampling delay: t
f (theoretical value) = f1 / (2(n + 1)) = 20 MHz / (2(25 + 1)) = 384.6 kbps
SCL
t = 1 / (2f
LOW SCL
t = 1 / (2f
HIGH SCL
= 1 / (2 × 384.6 kbps) + 100 ns + (1 × 1 / 20 MHz)
= 1.45 μs
f (actual value) = 1 / (t
SCL
Note:
1. Maximum 200 ns.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Change the internal clock
signal from high to low to
start counting low period
1 2
C mode is 50%. The low-level width of the SCL clock is 1.25 μ s
2
= minimum 1.3 μ s). Set the SCL clock to 384.6 kbps or less to
LOW
= 100 ns
R
= 0 ns
F
(1)
= 100 ns
NF
= 1 cycle
SD
(theoretical value)) = 1 / (2 × 384.6 kbps) = 1.3 μs
(theoretical value)) + t
NF
+ t + t + t
F LOW R
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Stop counting
3 4 5
Synchronized period
× 1 / f1)
+ (t
SD
) = 1 / (0 ns + 1.3 μs + 100 ns + 1.45 μs)
HIGH
Resume
counting
6 7 8 9
) into consideration.
R
~ ~
350.8 kbps
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