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M16C/64C Group
Table 17.9
Registers and Settings in Event Counter Mode (When Not Using Two-Phase Pulse
Signal Processing)
Register
PCLKR
CPSRF
PCLKSTP1
PWMFS
TACS0 to TACS2
TAPOFS
TAOW
TAi1
TABSR
ONSF
TRGSR
UDF
TAi
TAiMR
i = 0 to 4
Note:
1.
This table does not describe a procedure.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
(1)
Bit
PCLK0
- (setting unnecessary)
CPSR
Write 1 to reset the clock prescaler.
PCKSTP11
- (setting unnecessary)
PCKSTP17
- (setting unnecessary)
PWMFSi
Set to 0.
7 to 0
- (setting unnecessary)
Select the output polarity when the MR0 bit in the TAiMR
POFSi
register is 1 (pulse output).
TAiOW
Set to 0.
15 to 0
- (setting unnecessary)
Set to 1 when starting counting.
TAiS
Set to 0 when stopping counting.
TAiOS
Set to 0.
TAZIE
Set to 0.
TA0TGH to TA0TGL Select a count source.
TAiTGH to TAiTGL
Select a count source.
TAiUD
Select a count operation.
TAiP
Set to 0.
15 to 0
Set the counter value.
7 to 0
Refer to the TAiMR register below.
Function and Setting
17. Timer A
Page 275 of 807
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